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| L4904A DUAL 5V REGULATOR WITH RESET . . . . . . . . . . . . PRELIMINARY DATA OUTPUT CURRENTS : I01 = 50mA I02 = 100mA FIXED PRECISION OUTPUT VOLTAGE 5V 2 % RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE RESET FUNCTION EXTERNALLY PROGRAMMABLE TIMING RESET OUTPUT LEVEL RELATED TO OUTPUT 2 OUTPUT 2 INTERNALLY SWITCHED WITH ACTIVE DISCHARGING LOW LEAKAGE CURRENT, LESS THAN 1A AT OUTPUT 1 LOW QUIESCENT CURRENT (Input 1) INPUT OVERVOLTAGE PROTECTION UP TO 60V RESET OUTPUT NORMALLY HIGH OUTPUT TRANSISTORS SOA PROTECTION SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION Minidip ORDERING NUMBER : L4904A DESCRIPTION The L4904A is a monolithic low drop dual 5V regulator designed mainly for supplying microprocessor systems. Reset and data save functions during switch on/off can be realized. PIN CONNECTION July1993 1/9 L4904A PIN FUNCTIONS N 1 2 3 4 5 6 Name Input 1 Input 2 Timing Capacitor GND N.C. Reset Output Output 2 Output 1 Function Low Quiescent Current 50mA Regulator Input. 100mA Regulator Input. If Reg. 2 is switching-ON the delay capacitor is charged with a 10A constant current. When Reg. 2 is switched-OFF the delay capacitor is discharged. Common Ground. Not connected. When pin 3 reaches 5V the reset output is switched high. 5V Therefore tRD = Ct ( ); tRD (ms) = Ct (nF). 10A 5V - 100mA Regulator Output. Enabled if Vo 1 > VRT and VIN 2 > VIT. If Reg. 2 is switched-OFF the Co2 capacitor is discharged. 5V - 50mA regulator output with low leakage in switch-OFF condition. 7 8 BLOCK DIAGRAM SCHEMATIC DIAGRAM 2/9 L4904A ABSOLUTE MAXIMUM RATINGS Symbol VIN Io Ptot Tj Parameter DC Input Voltage Transient Input Overvoltage (t = 40ms) Output Current Power Dissipation at Tamb = 50C Storage and Junction Temperature Value 24 60 Internally Limited 1 - 40 to 150 Unit V V W C THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction-ambient Max Value 100 Unit C/W ELECTRICAL CHARACTERISTICS (VIN = 14.4V, Tamb = 25oC unless otherwise specified) Symbol Vi V01 V02 H V02 L I01 IL01 I02 VI01 VIT VITH V01 V02 V01 V02 IQ Parameter DC Operating Input Voltage Output Voltage 1 Output Voltage 2 HIGH Output Voltage 2 LOW Output Current 1 Leakage Output 1 Current Output Current 2 Output 1 Dropout Voltage (*) Input Threshold Voltage Input Threshold Voltage Hyst. Line Regulation Line Regulation 2 Load Regulation 1 Load Regulation 2 Quiescent Current Test Conditions R Load 1k R Load 1k I02 = - 5mA V01 = - 100mV VIN = 0, V01 3V V02 = - 100mV I01 = 10mA I01 = 50mA Min. 4.95 V01 -0.1 50 1 100 0.7 0.75 6.4 250 5 5 5 10 4.5 1.6 0.6 V02 -0.15 30 V02 - 1 3 4.9 50 4.12 0.25 0.8 0.9 V01 + 1.7 50 50 20 50 6.5 3.5 0.9 V02 - 0.05 80 V02 0.4 11 20 Typ. 5.05 5 0.1 Max. 20 5.15 V01 Unit V V V V mA A mA V V V mV mV mV mV mV mA V01 + 1.2 7V < VIN < 18V, I01 = 5mA 7V < VIN < 18V, I02 = 5mA VIN = 8V, 5mA < I01 < 50mA VIN = 8V, 5mA < I02 < 100mA I02 = I01 5mA 0 < VIN < 13V 7V < VIN < 13V 6.3V < VIN1 < 13V, VIN2 = 0 I01 5mA, I02 = 0 IQ1 VRT VRTH VRH VRL tRD td V01 T V02 T SVR1 SVR2 TJSD Quiescent Current 1 Reset Threshold Voltage Reset Threshold Hysteresis Reset Output Voltage HIGH Reset Output Voltage LOW Reset Pulse Delay Timing Capacitor Discharge Time Thermal Drift Thermal Drift Supply Voltage Rejection Supply Voltage Rejection Thermal Shut Down mA V mV V V ms s mV/C mV/C dB dB C IR = 500A IR = - 5mA Ct = 10nF Ct = 10nF - 20C <0>Tamb 125C - 20C <0>Tamb 125C f = 100Hz, VR = 0.5V, Io = 50mA f = 100Hz, VR = 0.5V, Io = 100mA 0.3 -0.8 0.3 - 0.8 50 50 84 80 150 * The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is lowered of 25 mV under constant output current condition. 3/9 L4904A TEST CIRCUIT Figure 1 : P.C. Board and Components Layout of the Test Circuit (1:1 scale) APPLICATION INFORMATION In power supplies for P systems it is necessary to provide power continuously to avoid loss of information in memories and in time of day clocks, or to savedata when the primary supply is removed. The L4904A makes it very easy to supply such equipments ; it provides two voltage regulators(booth 5V high precision) with separate inputs plus a reset output for the data save function. CIRCUIT OPERATION (see Figure 2) After switch on Reg. 1 saturates until V01 rises to the nominal value. When the input 2 reaches VIT and the output 1 is higher than VRT the output 2 (V02) switches on and the reset output (VR ) also goes high after a programmable time TRD (timing capacitor). V02 and VR are switched together at low level when one of the following conditions occurs : - an input overvoltage - an overload on the output 1 (V01 < VRT) ; - a switch off (VIN < VIT - VITH) ; and they start again as before when the condition is removed. 4/9 An overload on output 2 does not switch Reg. 2, and does not influence Reg. 1. The V01 output features : - 5 V internal reference without voltage divider between the output and the error comparator ; - very low drop series regulator element utilizing mirrors ; permit high output impedance and then very low leakage current even in power down conditions. This output may thereforebe used to supply circuits continuously, such as volatile RAMs, allowing the use of a back-up battery. The V01 regulator also features low consumption (0.6 mA typ.) to minimize battery drain in applications where the V1 regulator is permanently connected to a battery supply. The V02 output can supply other non essential 5 V circuits which may be powered down when the system is inactive, or that must be powered down to prevent uncorrect operation for supply voltages below the minimum value. The reset output can beused as a "POWER DOWN INTERRUPT", permitting RAM access only in correct power conditions, or as a "BACK-UP ENABLE" to transfer data into in a NV SHADOW MEMORY when the supply is interrupted. L4904A Figure 2 APPLICATION SUGGESTIONS Figure 3 shows an application circuit for a P system. Reg. 1 is permanently connected to a battery and supplies a CMOS time-of-day clock and a CMOS microcomputer chip with volatile memory. Reg. 2 may be switched OFF when the system is inactive. Figure 4 shows the L4904A with a back up battery on the V01 output to maintain a CMOS time-of-day clock and a stand by type C-MOS P. The reset Figure 3 output makes sure that the RAM is forced into the low consumption stand by state, so the access to memory is inhibit and the back up battery voltage cannot drop so low that memory contents are corrupted. In this case the main on-off switch disconnectsboth regulators from the supply battery. Application Circuits of a Microprocessor system (Figure 3) or with data save battery (Figure 4). The reset output provide delayed rising front at the turn-off of the regulator 2. 5/9 L4904A Figure 4 6/9 L4904A Figure 5 : Quiescent Current (reg. 1) versus Output Current Figure 6 : Quiescent Current (reg. 1 versus Input Voltage Figure 7 : Total Quiescent Current versus Input Voltage Figure 8 : Supply Voltage Rejection Regulators 1 and 2 versus Input Ripple Frequence 7/9 L4904A MINIDIP PACKAGE MECHANICAL DATA DIM. MIN. A a1 B b b1 D E e e3 e4 F I L Z 3.18 7.95 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.51 1.15 0.356 0.204 1.65 0.55 0.304 10.92 9.75 0.313 0.100 0.300 0.300 0.260 0.200 0.150 0.060 mm TYP. 3.32 0.020 0.045 0.014 0.008 0.065 0.022 0.012 0.430 0.384 MAX. MIN. inch TYP. 0.131 MAX. 8/9 L4904A Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 9/9 |
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